The present invention relates generally to computer memory, and more specifically to the configuration analysis of a computer main memory by a complex memory controller.
Memory interleaving is a technique which allows parallel or pipelined access of contiguous memory words in a computer memory bank. The goal of memory interleaving is to reduce the time required to perform a block access of computer main memory. Block accesses are useful for, e.g., fetching sequences of instructions or accessing linearly-ordered data structures.
Memory interleaving is accomplished by organizing a multi-row main memory bank such that contiguous memory addresses are spread across the rows. Thus, for example, if memory location n is in row 1, memory location n+1 is in row 2. Although each memory module, when presented with an address, can return only one memory word per cycle, if different addresses are presented to different memory modules simultaneously, or in a pipelined fashion, during a single memory cycle, a memory word can be returned from each. By organizing consecutive memory addresses across different rows, then, a contiguous block of memory can be accessed in one memory cycle. A memory configured to allow parallel or pipelined access of a block of m contiguous words is said to have m:1 interleaving.
Prior to the use of interleaving, computer memories were fairly straightforward to configure. Whenever a computer user desired to add a memory module to a computer memory board, he simply plugged it into the next available slot on the board.
Further memory modules were likewise added to the memory slots sequentially, until all slots were filled.
However, with the advent of memory systems which utilize interleaving and provide more complex main memories with, e.g., multiple memory banks, memory configuration has become more complex. Memory modules can be installed in various configurations in such systems, not all of which are equally desirable from a performance perspective. Some configurations, for example, may result in a higher memory interleaving value (and thus more efficient memory block accesses) than others. Furthermore, memory controllers in such complex memory systems, such as that in the Intel(copyright) 82450GX chipset, may place restrictions on memory configuration to enhance performance, including, e.g., restrictions regarding where additional memory modules can be installed and what types of modules (with respect to size, speed, etc.) can be used.
Thus, the configuration of a memory in a complex memory system can be a difficult task. While user manuals and other instructional materials supplied with complex memory boards provide guidance for the user as to allowable and optimal memory configurations, the user might not consult these materials prior to the installation of memory modules. If the user configures the memory improperly, some or all of the memory modules may be ignored by the computer""s memory controller and thus be rendered inoperative. The user may not realize that such performance deficiencies are a result of the memory configuration and may believe incorrectly that the computer system is defective. It is desired, then, to provide a capability for assessing a memory configuration and informing the user of errors and other performance data relating to that configuration.
The present invention provides a method and apparatus for analyzing the configuration of a computer main memory. A memory controller, which imposes restrictions on the memory""s configuration, determines whether a configuration is consistent with those restrictions. The results of the determination are then reported to the user.
In further embodiments of the present invention, the memory controller assesses a memory configuration""s compliance with interleave restrictions, memory row size restrictions, and memory speed restrictions. In addition to reporting restriction non-compliance, the memory controller can also assess and report whether a particular configuration is optimal.